The present invention relates to a technique which can advantageously be used for a verify method after write or erase and write or erase pulse application method in a non-volatile semiconductor memory electrically writable and erasable. For example, the present invention can effectively be used in a flash memory chip in which data can be erased on block basis at once and a microcomputer having such a flash memory built in.
A flash memory uses as a memory cell a non-volatile storage element including MOSFET of two-layered gate structure having a control gate and a floating gate. In such a flash memory, voltage is applied between a control gate and a substrate (or a well region) or between a control gate and a source or drain and electric charge is injected into or released into the floating gate, so as to change a threshold voltage, thereby storing data.
It should be noted that there are two types of flash memories: one in which the threshold voltage is increased for data write and decreased for data erase; and one in which the threshold voltage is decreased for write and increased for erase. In any of these, normally, write is performed in a word line unit (also called a sector unit) or the word line is divided into one to several hundreds of bytes for performing write while erase is performed on block base, i.e., a plurality of sectors sharing a well region and a source line are erased simultaneously.
We have examined details of the technique for reducing the time required for write a flash memory which employs the write method using hot electrons. Conventionally, when write or erase operation is performed in a flash memory, voltage is applied for write or erase and a verify read operation is performed to decide whether the memory threshold voltage has changed to a desired level. If the threshold voltage change is insufficient, again voltage is applied for write or erase. Control is performed by repeating the aforementioned operation, so that the threshold voltage distribution is not greater than the desired voltage or not smaller than the desired voltage.
However, while repeating the verify operation, memory cells in the vicinity of the threshold voltage allowance level may result in different decisions due to a noise coming into a sense amplifier and a slight difference of the operation condition. Moreover, there is also a case that electric charge is not completely injected into the floating gate and unstable charge trapped on the boundary of an insulation film causes decision that the threshold voltage has reached the desired level and after this, the verify operation is repeated while the charge on the insulation film boundary disappears, thereby changing the threshold voltage. For this, a memory cell which has once determined to be write complete or erase complete may be decided to be write complete or erase incomplete at the next verify operation. This results in increase of the total number of write and erase operations and the time required for write and erase, which may prevent convergence, i.e., the operation may not be terminated.
To solve the aforementioned problem, JP-A-2000-90675 laid-open on Mar. 31, 2000 proposes an invention that read is performed with a voltage of the verify condition mitigated (loosened) according to the number of times of application of write voltage to one and the same storage element. This prior art discloses an embodiment in which two stages of verify voltage are prepared and the two voltage levels are alternately used for performing the verify read and another embodiment in which at the last n-th time (fifth time for example), a voltage level with a mitigated condition is used for performing the verify read.
However, after further examination in details, we have found that there is a case that write operation or erase operation cannot be quickly converted only by switching the aforementioned two stages of verify voltage level. Moreover, even when a verify operation is performed with a mitigated voltage level, rewrite or re-erase may be performed, causing a phenomenon that the memory threshold voltage exceeds the allowable voltage level of the opposite side (hereinafter, referred to as Vth thrust).
Here, detailed explanation will be given on the aforementioned Vth thrust phenomenon with reference to FIG. 24. In FIG. 24, it is assumed that data xe2x80x9c0xe2x80x9d corresponds to a high threshold voltage of the memory cell and data xe2x80x9c1xe2x80x9d corresponds to a low threshold voltage of the memory cell; and the operation causing the memory cell to be in a high threshold voltage state is referred to as write while the operation causing the memory cell to be in a low threshold voltage state is referred to as erase. The embodiment of the present invention is based on this definition unless otherwise specified. Moreover, after decreasing a threshold voltage of a memory cell in a write state of a high threshold voltage, i.e., after erasing, a memory cell whose threshold voltage has been decreased too low is slightly increased in threshold voltage, which is referred to as post-erase (sometimes called rewrite depending on the documents but their meanings are identical). Moreover, the operation to lower a threshold voltage performed prior to the post-erase is referred to as erase.
As shown in FIG. 24, there is considered a case that the memory cell storing data xe2x80x9c1xe2x80x9d has a threshold voltage which should be between Ve1 and Ve2. We have examined a following method for rewriting data xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d in a flash memory. The threshold voltage of a memory cell having a high-state threshold voltage was made lower than the upper voltage allowance by the erase operation. After this, comparatively short write pulse was applied to or write is performed with a comparatively low voltage to those memory cells whose threshold voltage was lower than the lower voltage allowance level Ve1, thereby making the threshold voltage high. This post-erase operation is repeatedly performed, so that the memory cell which should store data xe2x80x9c1xe2x80x9d has a threshold voltage finally between Ve1 and Ve2.
As a result, if verify is performed with an identical voltage level (Ve1), a memory cell once decided to be xe2x80x9cgoodxe2x80x9d may be decided to be xe2x80x9cbadxe2x80x9d while the verify-is repeatedly performed. This xe2x80x9cbadxe2x80x9d memory cell is subjected to the post-erase and accordingly, its threshold voltage is increased by the next operation. As a result, on the contrary, the threshold voltage becomes too high exceeding the upper voltage allowance level Ve2, causing a xe2x80x9cthrustxe2x80x9d. This disables convergence of the erase operation.
FIG. 10 shows results of experiment we made. In the graph of FIG. 10, the horizontal axis represents a number of times that the post-erase was repeated; and
the vertical axis represents accumulated number of bits corresponding to all the bits to be erased. xe2x97xaf represents a bit whose threshold voltage is within the allowance range; ▪ represents a bit lower than the lower voltage allowance level Ve1, i.e., the bit to be post-erased; and ▴ represents a bit higher than the higher voltage allowance level Ve2, i.e., which has caused the xe2x80x9cthrustxe2x80x9d. As is clear from FIG. 10, when verify is performed with an identical voltage, the number of bits which cause the thrust is abruptly increased when the post-erase is repeated 14 times or more.
At this moment, there are still about 0.01% (for example, about 100 bits if the total number of bits is 1 M bits) of bits which are lower than the lower voltage allowance level Ve1 and accordingly, the post-erase cannot be terminated here. If these bits are left as they are, electric current flows into a non-selected memory cell, causing an error as read data. Moreover, when write operation is performed, the electric current is made to flow by this bit and correct write cannot be performed. Moreover, in a multi-value flash memory in which 2-bit data is stored in one memory cell, as show in FIG. 25, it is necessary that a distribution range of threshold voltage corresponding to each of the storage data be within a comparatively narrow range with a high accuracy. Accordingly, the verify decision becomes more strict than the two-value flash memory.
It is therefore an object of the present invention to provide non-volatile storage circuit such as a flash memory capable of reducing the total time required for erase or write and a semiconductor integrated circuit such as a microcomputer having the non-volatile storage circuit as a built-in component.
The aforementioned and other objects and characteristics of the present invention will be clear from the present specification and the attached drawings.
According to one aspect of the present invention, there is provided a non-volatile storage device comprising a control section and a memory array having a plurality of word lines and a plurality of memory cells connected to the respective word lines, wherein at least some of the memory cells have a threshold voltage contained in a first threshold voltage distribution among two or more threshold voltage distributions the control section selects a predetermined word line from the plurality of word lines, and performs: a first operation, i.e., the control section changes the threshold voltage of the plurality of memory cells connected to the selected word line, from the first threshold voltage distribution to a second threshold voltage distribution; and a second operation, i.e., control section checks whether the threshold voltage of the respective memory cells are contained in the second threshold voltage distribution. In the second operation, among the plurality of memory cells, those memory cells whose threshold voltage is not contained in the second threshold voltage distribution are subjected again to the first operation and the second operation. In the second operation, a predetermined voltage is applied to the respective memory cells, so as to check whether the threshold voltage of the memory cells are contained in the second threshold voltage distribution; and the predetermined voltage is provided in at least three levels. The predetermined voltage applied to memory cells in the second operation performed first is different from the predetermined voltage applied in the second operation performed later.
By the aforementioned aspect, the predetermined voltage used to check whether the threshold voltage of the memory cells is contained in a predetermined threshold voltage distribution is changed in three stages or more in a direction mitigating the decision condition. This prevent non-convergence of write and erase operation and reduce the time required for write and erase.
Moreover, in the decision operation (the second operation) to decide whether the threshold voltage of the memory cells is contained in a predetermined threshold voltage distribution, it is preferable that the predetermined voltage applied to the memory cells be gradually changed in a reverse direction against the change direction of the threshold voltage. This mitigates the decision condition to decide whether the threshold voltage of the memory cells is contained in the predetermined threshold voltage distribution, and increase the speed of convergence of the write and erase operation.
It is further preferable that the operation (first operation) for changing the first threshold voltage distribution to the second threshold voltage distribution be performed by applying a predetermined voltage to the memory cells and the voltage applied to the memory cells in the first operation which is performed later be different from the voltage applied to the memory cells in the first operation which has been performed first. Alternatively, it is possible that the time of the voltage application to the memory cells in the first operation performed later is set different from the time of voltage application to the memory cells in the first operation performed first. This effectively changes the threshold voltage of the memory cells and completes the write and erase in a short time.
According to another aspect of the present invention, the non-volatile storage device comprises a control section and a memory array section which includes a plurality of word lines and a plurality of memory cells connected to the respective word lines. Each of the memory cells has a threshold voltage contained in the first threshold voltage distribution among two ore more threshold voltage distributions. When the first threshold voltage distribution is higher than the second threshold voltage distribution, the control section performs the first operation to change to a threshold voltage lower than the upper limit of the second threshold voltage distribution. After this, those memory cells which have a threshold voltage lower than the lower limit of the second threshold voltage distribution detected in the second operation are changed in their threshold voltage to a threshold voltage higher than the lower voltage as a third operation and check is made to determine whether the respective threshold voltage of the memory cells are higher than the lower limit as a fourth operation. The third operation and the fourth operation are repeatedly performed. In the fourth operation, a predetermined voltage is applied to check whether the respective memory cells have a threshold voltage higher than the aforementioned lower limit. The predetermined voltage applied to the memory cells in the fourth operation performed first is made higher than the voltage equivalent to the lower limit of the second threshold voltage distribution. Alternatively, when the first threshold voltage distribution is lower than the second threshold voltage distribution, the fourth operation changes the predetermined voltage applied to the memory cells in the fourth operation performed first lower than the voltage equivalent to the upper limit of the second threshold voltage distribution. Thus, it is possible to prevent non-convergence of the write and erase, complete the write and erase in a short time, and reduce the threshold voltage distribution width and increase the read margin.
According to still another aspect of the present invention, there is provided a non-volatile storage system comprising a control device and one or more non-volatile storage devices, wherein the control device can set a first operation mode or a second operation mode in the non-volatile storage device(s); each of the non-volatile storage devices includes a control section and a memory array section; the memory array section has a plurality of word lines and a plurality of memory cells respectively connected to the word lines; each of the memory cells has a threshold voltage contained in a first threshold voltage distribution among two or more threshold voltage distributions. The control section selects a predetermined word line from the plurality of word lines, and performs: a first operation, i.e., the control section changes the threshold voltage of the plurality of memory cells connected to the selected word line, from the first threshold voltage distribution to a second threshold voltage distribution; and a second operation, i.e., control section checks whether the threshold voltage of the respective memory cells are contained in the second threshold voltage distribution. In the second operation, among the plurality of memory cells, those memory cells whose threshold voltage is not contained in the second threshold voltage distribution are subjected again to the first operation and the second operation. In the second operation, a predetermined voltage is applied to the respective memory cells, so as to check whether the threshold voltage of the memory cells are contained in the second threshold voltage distribution; the predetermined voltage is provided in at least three levels; and in the first operation mode, the predetermined voltage applied to a memory cell in the second operation is different from the predetermined voltage applied to the memory cell in the second operation performed later.
By the aforementioned aspect, the predetermined voltage used to check whether the threshold voltage of the memory cells is contained in a predetermined threshold voltage distribution is changed in at least three stages in the direction to mitigate the decision condition. This prevents non-convergence of write and erase operation and can complete write and erase in a short time, thereby realizing a system having a high throughput.